Intel reveals leap forward technology in transistor architecture

The leading technology harbor revealed what is believed to be a revolution in the transistor architecture technology, further highlighting that its plan on working to extend Moore’s Law to a trillion transistors on a package by 2030.

Continuing its footprints in creating world-changing technology in the world of mobile computing, unleashing capabilities of shaping new advanced generations of Moore’s law integration, Intel introduces the world the next evolution in transistor technology that is to open new horizon in the mobile computing scene.

During the 2023 IEEE International Electron Devices Meeting (IEDM), which took place earlier this week in San Francisco, Intel researchers showcased a 3D stack of the complementary metal oxide semiconductor transistors (CMOS) combined with backside power and direct backside contact, taking a leap in the future of processors with nearly double the density of transistors.

The newly introduced technology is based on new innovations of scaling more efficient transistors on silicon while, with combining them with backside power and backside contacts, which eventually achieve higher performance.

“At IEDM 2023, Intel showcases its progress with research advancements that fuel Moore’s Law,” said Sanjay Natarajan, Intel senior vice president and general manager of Components Research.

This comes underscoring our ability to bring leading-edge technologies that enable further scaling and efficient power delivery for the next generation of mobile computing, he added.

Through its announcement, the leading technology harbor revealed what is believed to be a revolution in the transistor architecture technology, further highlighting that its plan on working to extend Moore’s Law to a trillion transistors on a package by 2030.

“Before backside power delivery, processors were built in layers; starting with a single layer of devices and then adding multiple layers of metallic wires to interconnect them which requires smaller than smaller interconnects and more and more layers. Eventually this increases the cost,” Mauro Kobrinsky, Intel’s Director of Novel Interconnect Structures and Architectures explained.

Backside power delivery fundamentally changes the situation for the better, bringing a new interconnect era with a tremendous impact in lowering the process complexity, Kobrinsky added.

The importance of the game-changing technology lies in its essential role of exponentially increasing demand for more powerful computing.

Intel’s components researchers consistently push the boundaries of engineering by stacking transistors, taking backside power to the next level to enable more transistor scaling and improved performance, as well as demonstrating that transistors made of different materials can be integrated on the same wafer.